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tm 3-1 HFA1113 850mhz, low distortion, output limiting, programmable gain, buffer ampli?r the HFA1113 is a high speed buffer featuring user programmable gain and output limiting coupled with ultra high speed performance. this buffer is the ideal choice for high frequency applications requiring output limiting, especially those needing ultra fast overload recovery times. the output limiting function allows the designer to set the maximum positive and negative output levels, thereby protecting later stages from damage or input saturation. the sub-nanosecond overdrive recovery time quickly returns the ampli?r to linear operation following an overdrive condition. a unique feature of the pinout allows the user to select a voltage gain of +1, -1, or +2, without the use of any external components, as described in the ?pplication information section. compatibility with existing op amp pinouts provides ?xibility to upgrade low gain ampli?rs, while decreasing component count. unlike most buffers, the standard pinout provides an upgrade path should a higher closed loop gain be needed at a future date. component and composite video systems will also bene? from this buffers performance, as indicated by the excellent gain ?tness, and 0.02%/0.04 degree differential gain/phase speci?ations (r l = 150 ? ). for military product, refer to the HFA1113/883 data sheet. pinout HFA1113 (soic) top view features user programmable output voltage limiting user programmable for closed-loop gains of +1, -1 or +2 without use of external resistors wide -3db bandwidth. . . . . . . . . . . . . . . . . . . . . . 850mhz excellent gain flatness (to 100mhz). . . . . . . . . . 0.07db low differential gain and phase . . . 0.02%/0.04 degrees low distortion (hd3, 30mhz). . . . . . . . . . . . . . . . . -73dbc very fast slew rate . . . . . . . . . . . . . . . . . . . . . 2400v/ s fast settling time (0.1%) . . . . . . . . . . . . . . . . . . . . . 13ns high output current . . . . . . . . . . . . . . . . . . . . . . . . . 60ma excellent gain accuracy . . . . . . . . . . . . . . . . . . . 0.99v/v overdrive recovery . . . . . . . . . . . . . . . . . . . . . . . . . <1ns standard operational ampli?r pinout applications rf/if processors driving flash a/d converters high-speed communications impedance transformation line driving video switching and routing radar systems medical imaging systems ordering information part number (brand) temp. range ( o c) package pkg. no. HFA1113ib (h1113i) -40 to 85 8 ld soic m8.15 hfa11xxeval dip ev aluation board for high speed op amps nc -in +in v- 1 2 3 4 8 7 6 5 v h v+ out v l + 300 300 - pin descriptions name pin number description nc 1 no connection -in 2 inverting input +in 3 non-inverting input v- 4 negative supply v l 5 lower output limit out 6 output v+ 7 positive supply v h 8 upper output limit data sheet february 1999 file number 1342.5 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright intersil corporation 2000
3-2 absolute maximum ratings thermal information voltage between v+ and v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12v dc input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v supply voltage at v h or v l terminal . . . . . . . . . . . . . . (v+) + 2v to (v-) - 2v output current (50% duty cycle) . . . . . . . . . . . . . . . . . . . . . . 60ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 maximum junction temperature (plastic package) . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?ations v supply = 5v, a v = +1, r l = 100 ? , unless otherwise speci?d parameter test conditions temp. ( o c) min typ max units input characteristics output offset voltage 25 - 8 25 mv full - - 35 mv output offset voltage drift full - 10 - v/ o c psrr 25 39 45 - db full 35 - - db input noise voltage (note 3) 100khz 25 - 9 - nv/ hz +input noise current (note 3) 100khz 25 - 37 - pa/ hz non-inverting input bias current 25 - 25 40 a full - - 65 a non-inverting input resistance 25 25 50 - k ? inverting input resistance (note 2) 25 240 300 360 ? input capacitance 25 - 2 - pf input common mode range full 2.5 2.8 - v transfer characteristics gain a v = +1, v in = +2v 25 0.980 0.990 1.020 v/v full 0.975 - 1.025 v/v a v = +2, v in = +1v 25 1.96 1.98 2.04 v/v full 1.95 - 2.05 v/v dc non-linearity (note 3) a v = +2, 2v full scale 25 - 0.02 - % output characteristics output voltage (note 3) a v = -1 25 3.0 3.3 - v full 2.5 3.0 - v output current (note 3) r l = 50 ? 25, 85 50 60 - ma -40 35 50 - ma closed loop output impedance dc, a v = +2 25 - 0.3 - ? power supply characteristics supply voltage range full 4.5 - 5.5 v supply current (note 3) 25 - 21 26 ma full - - 33 ma HFA1113
3-3 ac characteristics -3db bandwidth (v out = 0.2v p-p , notes 2, 3) a v = -1 25 450 800 - mhz a v = +1 25 500 850 - mhz a v = +2 25 350 550 - mhz slew rate (v out = 5v p-p , note 2) a v = -1 25 1500 2400 - v/ s a v = +1 25 800 1500 - v/ s a v = +2 25 1100 1900 - v/ s full power bandwidth (v out = 5v p-p , note 3) a v = -1 25 - 300 - mhz a v = +1 25 - 150 - mhz a v = +2 25 - 220 - mhz gain flatness (to 30mhz, notes 2, 3) a v = -1 25 - 0.02 - db a v = +1 25 - 0.1 - db a v = +2 25 - 0.015 0.04 db gain flatness (to 50mhz, notes 2, 3) a v = -1 25 - 0.05 - db a v = +1 25 - 0.2 - db a v = +2 25 - 0.036 0.08 db gain flatness (to 100mhz, notes 2, 3) a v = -1 25 - 0.10 - db a v = +2 25 - 0.07 0.22 db linear phase deviation (to 100mhz, note 3) a v = -1 25 - 0.13 - degrees a v = +1 25 - 0.83 - degrees a v = +2 25 - 0.05 - degrees 2nd harmonic distortion (30mhz, v out = 2v p-p , notes 2, 3) a v = -1 25 - -52 - dbc a v = +1 25 - -57 - dbc a v = +2 25 - -52 -45 dbc 3rd harmonic distortion (30mhz, v out = 2v p-p , notes 2, 3) a v = -1 25 - -71 - dbc a v = +1 25 - -73 - dbc a v = +2 25 - -72 -65 dbc 2nd harmonic distortion (50mhz, v out = 2v p-p , notes 2, 3) a v = -1 25 - -47 - dbc a v = +1 25 - -53 - dbc a v = +2 25 - -47 -40 dbc 3rd harmonic distortion (50mhz, v out = 2v p-p , notes 2, 3) a v = -1 25 - -63 - dbc a v = +1 25 - -68 - dbc a v = +2 25 - -65 -55 dbc 2nd harmonic distortion (100mhz, v out = 2v p-p , notes 2, 3) a v = -1 25 - -41 - dbc a v = +1 25 - -50 - dbc a v = +2 25 - -42 -35 dbc 3rd harmonic distortion (100mhz, v out = 2v p-p , notes 2, 3) a v = -1 25 - -55 - dbc a v = +1 25 - -49 - dbc a v = +2 25 - -62 -45 dbc electrical speci?ations v supply = 5v, a v = +1, r l = 100 ? , unless otherwise speci?d (continued) parameter test conditions temp. ( o c) min typ max units HFA1113
3-4 3rd order intercept (a v = +2, note 3) 100mhz 25 - 28 - dbm 300mhz 25 - 13 - dbm 1db compression (a v = +2, note 3) 100mhz 25 - 19 - dbm 300mhz 25 - 12 - dbm reverse isolation (s 12 , note 3) 40mhz 25 - -70 - db 100mhz 25 - -60 - db 600mhz 25 - -32 - db transient characteristics rise time (v out = 0.5v step, note 2) a v = -1 25 - 500 800 ps a v = +1 25 - 480 750 ps a v = +2 25 - 700 1000 ps rise time (v out = 2v step) a v = -1 25 - 0.82 - ns a v = +1 25 - 1.06 - ns a v = +2 25 - 1.00 - ns overshoot (v out = 0.5v step, input t r /t f = 200ps, notes 2, 3, 4) a v = -1 25 - 12 30 % a v = +1 25 - 45 65 % a v = +2 25 - 6 20 % 0.1% settling time (note 3) v out = 2v to 0v 25 - 13 20 ns 0.05% settling time v out = 2v to 0v 25 - 20 33 ns differential gain a v = +1, 3.58mhz, r l = 150 ? 25 - 0.03 - % a v = +2, 3.58mhz, r l = 150 ? 25 - 0.02 - % differential phase a v = +1, 3.58mhz, r l = 150 ? 25 - 0.05 - degrees a v = +2, 3.58mhz, r l = 150 ? 25 - 0.04 - degrees output limiting characteristics a v = +2, v h = +1v, v l = -1v, unless otherwise speci?d clamp accuracy (note 3) v in = 1.6v, a v = -1 25 - 100 150 mv full - - 200 mv clamp overshoot v in = 1v, input t r /t f = 500ps 25 - 7 - % overdrive recovery time (note 3) v in = 1v 25 - 0.75 1.5 ns negative clamp range 25 - -5.0 to +2.0 -v positive clamp range 25 - -2.0 to +5.0 -v clamp input bias current (note 3) 25 - 50 200 a full - - 300 a clamp input bandwidth (note 3) v h or v l = 100mv p-p 25 - 500 - mhz notes: 2. this parameter is not tested. the limits are guaranteed based on lab characterization, and reflect lot-to-lot variation. 3. see typical performance curves for more information. 4. overshoot decreases as input transition times increase, especially for a v = +1. please refer to typical performance curves. electrical speci?ations v supply = 5v, a v = +1, r l = 100 ? , unless otherwise speci?d (continued) parameter test conditions temp. ( o c) min typ max units HFA1113
3-5 application information closed loop gain selection the HFA1113 features a novel design which allows the user to select from three closed loop gains, without any external components. the result is a more ?xible product, fewer part types in inventory, and more ef?ient use of board space. this ?uffer?operates in closed loop gains of -1, +1, or +2, and gain selection is accomplished via connections to the inputs. applying the input signal to +in and floating -in selects a gain of +1, while grounding -in selects a gain of +2. a gain of -1 is obtained by applying the input signal to -in with +in grounded. the table below summarizes these connections: pc board layout the frequency response of this ampli?r depends greatly on the amount of care taken in designing the pc board. the use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! attention should be given to decoupling the power supplies. a large value (10 f) tantalum in parallel with a small value chip (0.1 f) capacitor works well in most cases. terminated microstrip signal lines are recommended at the input and output of the device. capacitance directly on the output must be minimized, or isolated as discussed in the next section. for unity gain applications, care must also be taken to minimize the capacitance to ground seen by the ampli?rs inverting input. at higher frequencies this capacitance will tend to short the -input to gnd, resulting in a closed loop gain which increases with frequency. this will cause excessive high frequency peaking and potentially other problems as well. an example of a good high frequency layout is the evaluation board shown in figure 3. driving capacitive loads capacitive loads, such as an a/d input, or an improperly terminated transmission line will degrade the ampli?rs phase margin resulting in frequency response peaking and possible oscillations. in most cases, the oscillation can be avoided by placing a resistor (r s ) in series with the output prior to the capacitance. figure 1 details starting points for the selection of this resistor. the points on the curve indicate the r s and c l combinations for the optimum bandwidth, stability, and settling time, but experimental ?e tuning is recommended. picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. r s and c l form a low pass network at the output, thus limiting system bandwidth well below the ampli?r bandwidth of 850mhz. by decreasing r s as c l increases (as illustrated in the curves), the maximum bandwidth is obtained without sacri?ing stability. even so, bandwidth does decrease as you move to the right along the curve. for example, at a v = +1, r s = 50 ? , c l = 30pf, the overall bandwidth is limited to 300mhz, and bandwidth drops to 100mhz at a v = +1, r s = 5 ? , c l = 340pf. evaluation board the performance of the HFA1113 may be evaluated using the hfa11xx evaluation board, slightly modi?d as follows: 1. remove the 500 ? feedback resistor (r 2 ), and leave the connection open. 2. a. for a v = +1 evaluation, remove the 500 ? gain setting resistor (r 1 ), and leave pin 2 ?ating. b. for a v = +2, replace the 500 ? gain setting resistor with a 0 ? resistor to gnd. the modi?d schematic and layout of the board are shown in figures 2 and 3. to order evaluation boards (part number hfa11xxeval), please contact your local sales of?e. note: the soic version may be evaluated in the dip board by using a soic-to-dip adapter such as aries electronics part number 08-350000-10. gain (a cl ) connections +input (pin 3) -input (pin 2) -1 gnd input +1 input nc (floating) +2 input gnd r s ( ? ) load capacitance (pf) 50 45 40 35 30 25 20 15 10 5 0 0 40 80 120 160 200 240 280 320 360 400 a v = +1 a v = +2 figure 1. recommended series resistor vs load capacitance HFA1113
3-6 . limiting operation general the HFA1113 features user programmable output clamps to limit output voltage excursions. clamping action is obtained by applying voltages to the v h and v l terminals (pins 8 and 5) of the ampli?r. v h sets the upper output limit, while v l sets the lower clamp level. if the ampli?r tries to drive the output above v h , or below v l , the clamp circuitry limits the output voltage at v h or v l ( the clamp accuracy), respectively. the low input bias currents of the clamp pins allow them to be driven by simple resistive divider circuits, or active elements such as ampli?rs or dacs. clamp circuitry figure 4 shows a simpli?d schematic of the HFA1113 input stage, and the high clamp (v h ) circuitry. as with all current feedback ampli?rs, there is a unity gain buffer (q x1 - q x2 ) between the positive and negative inputs. this buffer forces -in to track +in, and sets up a slewing current of: (v -in - v out )/r f + v -in /r g this current is mirrored onto the high impedance node (z) by q x3 -q x4 , where it is converted to a voltage and fed to the output via another unity gain buffer. if no clamping is utilized, the high impedance node may swing within the limits de?ed by q p4 and q n4 . note that when the output reaches its quiescent value, the current ?wing through -in is reduced to only that small current (-i bias ) required to keep the output at the ?al voltage. tracing the path from v h to z illustrates the effect of the clamp voltage on the high impedance node. v h decreases by 2v be (q n6 and q p6 ) to set up the base voltage on q p5 . q p5 begins to conduct whenever the high impedance node reaches a voltage equal to q p5 s base voltage + 2v be (q p5 and q n5 ). thus, q p5 clamps node z whenever z reaches v h . r 1 provides a pull-up network to ensure functionality with the clamp inputs ?ating. a similar description applies to the symmetrical low clamp circuitry controlled by v l . when the output is clamped, the negative input continues to source a slewing current (i clamp ) in an attempt to force the output to the quiescent voltage de?ed by the input. q p5 must sink this current while clamping, because the -in current is always mirrored onto the high impedance node. the clamping current is calculated as: i clamp = (v -in - v out clamped )/300 ? + v -in /r g . as an example, a unity gain circuit with v in = 2v, and v h =1v, would have i clamp = (2v - 1v)/300 ? + 2v/ = 3.33ma (r g = because -in is floated for unity gain applications). note that i cc will increase by i clamp when the output is clamp limited. 1 2 3 4 8 7 6 5 +5v 10 f 0.1 f v h 50 ? gnd gnd r 1 -5v 0.1 f 0 f 50 ? in out v l (a v = +1) or 0 ? (a v = +2) figure 2. modified evaluation board schematic v h +in v l v+ gnd 1 v- out top layout bottom layout figure 3. evaluation board layout +1 +in v- v+ q p1 q n1 v- q n3 q p3 q p4 q n2 q p2 q n4 q p5 q n5 z v+ -in v out i clamp r f = 300 ? (internal) q p6 q n6 v h r 1 50k (30k for v l ) 300 ? r g (internal) v -in 200 ? figure 4. HFA1113 simplified v h clamp circuitry HFA1113
3-7 clamp accuracy the clamped output voltage will not be exactly equal to the voltage applied to v h or v l . offset errors, mostly due to v be mismatches, necessitate a clamp accuracy parameter which is found in the device speci?ations. clamp accuracy is a function of the clamping conditions. referring again to figure 4, it can be seen that one component of clamp accuracy is the vbe mismatch between the q x6 transistors, and the q x5 transistors. if the transistors always ran at the same current level there would be no v be mismatch, and no contribution to the inaccuracy. the q x6 transistors are biased at a constant current, but as described earlier, the current through q x5 is equivalent to i clamp . v be increases as i clamp increases, causing the clamped output voltage to increase as well. i clamp is a function of the overdrive level (a vcl x v in - v out clamped ), so clamp accuracy degrades as the overdrive increases. as an example, the speci?d accuracy of 100mv (a v = -1, v h = 1v) for a 1.6x overdrive degrades to 240mv for a 3x (200%) overdrive, as shown in figure 43. consideration must also be given to the fact that the clamp voltages have an affect on ampli?r linearity. the ?onlinearity near clamp voltage?curve, figure 48, illustrates the impact of several clamp levels on linearity. clamp range unlike some competitor devices, both v h and v l have usable ranges that cross 0v. while v h must be more positive than v l , both may be positive or negative, within the range restrictions indicated in the speci?ations. for example, the HFA1113 could be limited to ecl output levels by setting v h = -0.8v and v l = -1.8v. v h and v l may be connected to the same voltage (gnd for instance) but the result won? be in a dc output voltage from an ac input signal. a 150mv - 200mv ac signal will still be present at the output. recovery from overdrive the output voltage remains at the clamp level as long as the overdrive condition remains. when the input voltage drops below the overdrive level (v clamp /a vcl ) the ampli?r will return to linear operation. a time delay, known as the overdrive recovery time, is required for this resumption of linear operation. the plots of ?nclamped performance and ?lamped performance?(figures 41 and 42) highlight the HFA1113s subnanosecond recovery time. the difference between the unclamped and clamped propagation delays is the overdrive recovery time. the appropriate propagation delays are 8.0ns for the unclamped pulse, and 8.8ns for the clamped (2x overdrive) pulse yielding an overdrive recovery time of 800ps. the measurement uses the 90% point of the output transition to ensure that linear operation has resumed. note: the propagation delay illustrated is dominated by the ?turing. the delta shown is accurate, but the true HFA1113 propagation delay is 500ps. overdrive recovery time is also a function of the overdrive level. figure 47 details the overdrive recovery time for various clamp and overdrive levels. typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise speci?d figure 5. small signal pulse response figure 6. large signal pulse response a v = +2 200 150 100 50 0 -50 -100 -150 -200 output voltage (mv) time (5ns/div.) a v = +2 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 output voltage (v) time (5ns/div.) HFA1113
3-8 figure 7. small signal pulse response figure 8. large signal pulse response figure 9. small signal pulse response figure 10. large signal pulse response figure 11. frequency response figure 12. frequency response for various load resistors typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise speci?d (continued) a v = +1 200 150 100 50 0 -50 -100 -150 -200 output voltage (mv) time (5ns/div.) a v = +1 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 output voltage (v) time (5ns/div.) a v = -1 200 150 100 50 0 -50 -100 -150 -200 output voltage (mv) time (5ns/div.) a v = -1 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 output voltage (v) time (5ns/div.) normalized gain (db) 6 3 0 -3 -6 -9 0.3 1 10 100 1000 normalized phase (degrees) frequency (mhz) v out = 200mv p-p 0 -90 -180 -270 -360 gain phase a v = +1 a v = +1 a v = +2 a v = -1 a v = -1 a v = +2 gain (db) 0.3 1 10 100 1000 phase (degrees) frequency (mhz) 9 6 3 0 0 -90 -180 -270 -360 r l = 100 ? r l = 1k ? r l = 50 ? gain phase a v = +2, v out = 200mv p-p r l = 1k ? r l = 100 ? r l = 50 ? HFA1113
3-9 figure 13. frequency response for various load resistors figure 14. frequency response for various load resistors figure 15. frequency response for various output voltages figure 16. frequency response for various output voltages figure 17. frequency response for various output voltages figure 18. full power bandwidth typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise speci?d (continued) gain (db) 0.3 1 10 100 1000 0 -90 -180 -270 -360 phase (degrees) frequency (mhz) a v = +1, v out = 200mv p-p 6 3 0 -3 -6 -9 gain phase r l = 1k ? r l = 50 ? r l = 100 ? r l = 100 ? r l = 50 ? r l = 1k ? gain (db) 180 90 0 -90 -180 phase (degrees) 6 3 0 -3 -6 -9 a v = -1, v out = 200mv p-p r l = 100 ? r l = 100 ? r l = 50 ? r l = 1k ? 0.3 1 10 100 1000 frequency (mhz) gain phase r l = 1k ? r l = 50 ? gain (db) 12 9 6 3 0 0 -90 -180 -270 -360 phase (degrees) a v = +2 1v p-p gain phase 0.3 1 10 100 1000 frequency (mhz) 4.0v p-p 2.5v p-p 4.0v p-p 2.5v p-p 1v p-p gain (db) 0 -90 -180 -270 -360 phase (degrees) 6 3 0 -3 -6 a v = +1 gain phase 0.3 1 10 100 1000 frequency (mhz) v out = 1v p-p v out = 2.5v p-p v out = 4v p-p v out = 1v p-p v out = 2.5v p-p v out = 4v p-p gain (db) 180 90 0 -90 -180 phase (degrees) 6 3 0 -3 -6 a v = -1 gain phase 0.3 1 10 100 1000 frequency (mhz) v out = 1v p-p v out = 2.5v p-p v out = 4v p-p v out = 1v p-p v out = 2.5v p-p v out = 4v p-p normalized gain (db) 15 12 9 6 3 0 -3 -6 -9 -12 -15 0.3 1 10 100 1000 frequency (mhz) v out = 5v p-p a v = +1 a v = +2 a v = -1 HFA1113
3-10 figure 19. -3db bandwidth vs temperature figure 20. gain flatness figure 21. deviation from linear phase figure 22. settling response figure 23. low frequency reverse isolation (s 12 ) figure 24. high frequency reverse isolation (s 12 ) typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise speci?d (continued) bandwidth (mhz) 900 850 800 750 700 650 600 550 500 -50 -25 0 25 50 75 100 125 temperature ( o c) a v = -1 a v = +1 a v = +2 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 1 10 100 frequency (mhz) normalized gain (db) a v = -1 a v = +1 a v = +2 4 3 2 1 0 -1 -2 -3 -4 -5 -6 0 15 30 45 60 75 90 105 120 135 frequency (mhz) deviation (degrees) a v = -1 a v = +1 a v = +2 150 settling error (%) 0.6 0.4 0.2 0.1 0 -0.1 -0.2 -0.4 -0.6 -2 3 8 13 18 23 28 33 38 43 48 time (ns) a v = +2, v out = 2v -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 gain (db) 20 40 60 80 100 120 140 160 180 200 frequency (mhz) a v = +1 a v = -1 a v = +2 a v = +2 0 a v = -1 gain (db) -24 -30 -36 -42 -48 -54 -60 100 190 280 370 460 550 640 730 820 910 1000 frequency (mhz) phase (degrees) 235 180 90 45 0 a v = +2 a v = -1 gain phase a v = -1 a v = +1 a v = +2 a v = -1 HFA1113
3-11 figure 25. 1db gain compression vs frequency figure 26. third order intermodulation intercept vs frequency figure 27. second harmonic distortion vs p out figure 28. third harmonic distortion vs p out figure 29. second harmonic distortion vs p out figure 30. third harmonic distortion vs p out typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise speci?d (continued) output power at 1db compression (dbm) 20 18 16 14 12 10 8 6 4 2 0 100 200 300 400 500 frequency (mhz) a v = +2 a v = +1 a v = -1 30 20 10 0 intercept point (dbm) 100 200 300 400 2 - tone frequency (mhz) a v = -1 a v = +1 a v = +2 -20 -30 -40 -50 -60 -70 -80 -90 -100 -6 -3 0 3 6 9 12 15 output power (dbm) distortion (dbc) a v = +2 100mhz 50mhz 30mhz -20 -30 -40 -50 -60 -70 -80 -90 -100 distortion (dbc) -6 -3 0 3 6 9 12 15 18 output power (dbm) a v = +2 100mhz 50mhz 30mhz -20 -30 -6 -3 0 3 6 9 12 15 distortion (dbc) output power (dbm) -40 -50 -60 -70 -80 -90 -100 a v = +1 100mhz 50mhz 30mhz distortion (dbc) a v = +1 100mhz 50mhz 30mhz -20 -30 -6 -3 0 3 6 9 12 15 output power (dbm) -40 -50 -60 -70 -80 -90 -100 HFA1113
3-12 figure 31. second harmonic distortion vs p out figure 32. third harmonic distortion vs p out figure 33. integral linearity error figure 34. overshoot vs input rise time figure 35. overshoot vs input rise time figure 36. overshoot vs input rise time typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise speci?d (continued) distortion (dbc) -20 -30 -6 -3 0 3 6 9 12 15 output power (dbm) -40 -50 -60 -70 -80 -90 -100 100mhz 50mhz 30mhz a v = -1 distortion (dbc) -20 -30 -6 -3 0 3 6 9 12 15 output power (dbm) -40 -50 -60 -70 -80 -90 -100 100mhz 50mhz 30mhz a v = -1 -3.0 input voltage (v) -2.0 -1.0 0 1.0 2.0 3.0 -0.04 -0.02 0 0.02 0.04 percent error (%) 100 300 500 700 900 1100 1300 overshoot (%) input rise time (ps) 60 50 40 30 20 10 0 v out = 0.5v a v = +1 a v = -1 a v = +2 100 300 500 700 900 1100 1300 overshoot (%) input rise time (ps) 60 50 40 30 20 10 0 v out = 1v a v = +1 a v = -1 a v = +2 60 50 40 30 20 10 0 100 300 500 700 900 1100 1300 overshoot (%) input rise time (ps) v out = 2v a v = +1 a v = +2 a v = -1 HFA1113
3-13 figure 37. supply current vs supply voltage figure 38. supply current vs temperature figure 39. output voltage vs temperature figure 40. input noise characteristics figure 41. unclamped performance figure 42. clamped performance typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise speci?d (continued) total supply voltage (v+ - v-, v) 22 17 15 13 11 supply current (ma) 59 9 7 5 678 10 21 20 19 6 8 10 12 14 16 18 25 24 23 22 21 20 19 18 17 16 15 -50 -25 0 25 50 75 100 125 temperature ( o c) supply current (ma) 3.6 3.5 3.4 3.3 3.2 3.1 2.9 2.8 2.7 2.6 -50 -25 0 25 50 75 100 125 temperature ( o c) output voltage (v) a v = -1 +v out (r l = 50 ?) |-v out | (r l = 100 ?) |-v out | (r l = 50 ?) 3.0 +v out (r l = 100 ?) 50 40 30 20 10 130 110 90 70 50 30 0.1 1 10 100 frequency (khz) noise voltage (nv/ hz) 0 noise current (pa/ hz) e ni i ni in 0v to 0.5v a v = +2 out 0v to 1v time (20ns/div.) in 0v to 1v a v = +2 out 0v to 1v time (20ns/div.) HFA1113
3-14 figure 43. v h clamp accuracy vs overdrive figure 44. v l clamp accuracy vs overdrive figure 45. v h clamp accuracy vs overdrive figure 46. v l clamp accuracy vs overdrive figure 47. overdrive recovery vs overdrive figure 48. non-linearity near clamp voltage typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise speci?d (continued) 0 100 200 300 400 500 0 50 100 150 200 250 300 350 a v = 1 overdrive (% of v h ) clamp accuracy (mv) v h = 100mv v h = 2v v h = 1v v h = 500mv v l = -500mv 0 100 200 300 400 500 0 50 100 150 200 250 a v = 1 overdrive (% of v l ) clamp accuracy (mv) v l = -100mv v l = -1v v l = -2v v h = 500mv 0 100 200 300 400 500 0 100 200 300 400 overdrive (% of v h ) clamp accuracy (mv) v h = 100mv v h = 2v v h = 1v a v = 2 0 100 200 300 400 500 0 50 100 150 200 250 overdrive (% of v l ) clamp accuracy (mv) v l = -1v v l = -2v a v = +2 v l = -500mv v l = -100mv 100 200 300 400 500 0 500 1000 1500 2000 2500 3000 3500 overdrive level (% of clamp level) overdrive recovery time (ps) v h = 1v v h = 2v v h = 0.5v v h = 0.1v 20 15 10 5 0 -5 -10 -15 -20 v out - (a v x v in ) (mv) -3 -2 -1 0 1 2 3 a v x v in (v) v l = -3v v l = -1v v l = -2v v h = 3v v h = 1v v h = 2v a v = -1 HFA1113
3-15 figure 49. clamp accuracy vs temperature figure 50. clamp bias current vs temperature figure 51. v h clamp input bandwidth figure 52. v l clamp input bandwidth typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ? , unless otherwise speci?d (continued) -50 0 50 100 150 60 70 80 90 100 110 120 130 140 temperature ( o c) clamp accuracy (mv) a v = -1, v in = 1.6v v h = 1v, v l = -1v v h v l 125 75 25 -25 -75 20 30 40 50 60 70 80 90 100 110 120 130 temperature ( o c) clamp bias current ( a) v h = 1v, v l = -1v v l v h -50 0 50 100 150 125 75 25 -25 -75 frequency (mhz) 1 10 100 1000 v h = 600mv p-p v h = 1.2v p-p v h = 300mv p-p 6 3 0 -3 -6 -9 -12 gain (db) frequency (mhz) 1 10 100 1000 v l = 600mv p-p v l = 1.2v p-p v l = 300mv p-p 6 3 0 -3 -6 -9 -12 gain (db) HFA1113
3-16 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com die characteristics die dimensions: 63 mils x 44 mils x 19 mils 1600 m x 1130 m x 483 m metallization: type: metal 1: aicu(2%)/tiw thickness: metal 1: 8k ? 0.4k ? type: metal 2: aicu(2%) thickness: metal 2: 16k ? 0.8k ? passivation: type: nitride thickness: 4k ? 0.5k ? transistor count: 52 substrate potential (powered up): floating (recommend connection to v-) metallization mask layout HFA1113 nc v- v l nc out +in -in v h v+ HFA1113

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